Processor Fundamentals

The central processing unit (CPU) fetches instructions from memory and carries them out, one after another. This chapter explains how it is organised, what it does in each cycle, how a low-level program is written, and how individual bits are manipulated. The register transfer notation and assembly questions are very mark-heavy in Paper 1, so practise tracing them until you can do it without errors.

4.1 Central Processing Unit (CPU) architecture

The Von Neumann model and the stored program concept

In the Von Neumann architecture, both the program instructions and the data are stored in the same main memory, as binary, and are fetched along the same buses. This is the stored program concept: a computer's behaviour is changed by loading a different program into memory, rather than by rewiring the hardware. The processor fetches one instruction at a time and processes it in sequence.

The main components are the processor (containing the ALU, control unit and registers), main memory (the immediate access store, IAS), input and output devices, and the buses that join them.

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The Von Neumann model: the CPU holds the control unit, ALU, system clock and registers PC, MAR, MDR, CIR, ACC, IX and SR; main memory and the input and output devices connect to it by the address bus, the data bus and the control bus

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Registers

A register is a small, very fast storage location inside the processor. A general purpose register can be used by the programmer for any data (for example the accumulator). A special purpose register has a particular job in the processor.

ALU, control unit, system clock and IAS

• The Arithmetic and Logic Unit (ALU) carries out calculations (add, subtract, multiply, shift) and logical comparisons (AND, OR, NOT, compare).
• The Control Unit (CU) fetches and decodes instructions and controls the other components by sending control signals. It manages the timing of the fetch-execute cycle.
• The system clock produces a regular stream of pulses that synchronises all the operations of the computer. The clock speed (in hertz) is the number of cycles per second.
• The immediate access store (IAS) is the main memory, the RAM that holds the programs and data currently in use and can be accessed directly by the processor.

Buses

A bus is a set of parallel wires (one per bit) that carries signals between components.

• The address bus carries the address of the memory location or device to be accessed. It is one-way, from the processor to memory. Its width decides how many locations can be addressed ($2^{\text{width}}$).
• The data bus carries the data and instructions. It is two-way. Its width decides how many bits can be moved at once.
• The control bus carries control signals (for example memory read, memory write, clock, interrupt request and acknowledge). It is two-way, because the processor sends commands and receives signals such as interrupts.

Factors that affect performance

• Clock speed: a faster clock means more instruction cycles per second. Increasing it also makes the processor hotter.
• Number of cores: each core can carry out its own instructions, so a multi-core processor can run several tasks at once. A program must be designed to share work between cores to benefit fully.
• Cache memory: a small amount of very fast memory (SRAM) on or near the CPU that stores frequently used data and instructions, so the processor does not wait for slower main memory. More cache, or cache at a closer level, generally improves performance.
• Bus width: a wider data bus moves more bits per transfer, and a wider address bus allows more memory to be addressed.
• Word length (the number of bits processed at once) and the amount of RAM also matter: too little RAM causes slow transfers to the disk (virtual memory).

Ports

A port is a socket through which a peripheral device connects to the computer.

• USB (Universal Serial Bus): a standard connection for many devices (keyboard, flash drive, printer). It transmits data serially, supplies power, and is hot-swappable.
• HDMI (High-Definition Multimedia Interface): carries digital video and audio to a monitor or television.
• VGA (Video Graphics Array): an older analogue video connection to a monitor; it carries video only.

The Fetch-Execute cycle

The processor repeats this cycle for every instruction. In register transfer notation (RTN), [x] means "the contents of x" and ← means "is copied to".

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The fetch stage: step 1 copies the address in the PC to the MAR, step 2 adds 1 to the PC, step 3 reads the instruction at that address into the MDR along the data bus, and step 4 copies it to the CIR, where the control unit decodes it

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Fetch

1. The address of the next instruction is copied from the PC to the MAR: MAR ← [PC]
2. The PC is incremented so it points to the next instruction: PC ← [PC] + 1
3. The instruction at that address is copied from memory (along the data bus) to the MDR: MDR ← [[MAR]]
4. The instruction is copied from the MDR to the CIR: CIR ← [MDR]

Decode: the control unit decodes the instruction in the CIR, splitting it into the opcode (what to do) and operand (what to do it with, such as an address or value).

Execute: the instruction is carried out. The ALU performs a calculation, data is moved between registers or memory, or the PC is changed (for a jump). For a memory read the operand address goes to the MAR and the data comes back to the MDR and then to the ACC.

Interrupts

An interrupt is a signal sent to the processor to say that something needs attention immediately.

Sources include hardware (a key pressed, a mouse click, a printer out of paper), software (an error such as division by zero, a program request for an OS service) and timer signals (the end of a process's time slice, in multitasking).

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Flowchart of interrupt handling: at the end of each fetch-execute cycle the processor checks for an interrupt; if there is none it continues, and if there is a higher priority one it saves the PC and registers on a stack, runs the interrupt service routine, restores them and resumes the program

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How an interrupt is handled:

1. At the end of each fetch-execute cycle, the processor checks for an interrupt (the interrupt flag or interrupt register).
2. If one is present, and its priority is higher than the current task, the processor stops what it is doing. The current register contents (the PC and the other registers) are saved on a stack.
3. The processor runs the appropriate interrupt service routine (ISR), found by looking up the interrupt type.
4. When the ISR has finished, the saved values are restored from the stack, and the original program carries on from where it stopped.

If several interrupts occur, they are processed in order of priority. Interrupts let the processor respond quickly without wasting time repeatedly checking each device (polling).

4.2 Assembly language

Machine code and assembly language

Machine code is the binary instructions that the processor executes directly. Each instruction is made of an opcode and an operand. Assembly language is a low-level language that uses mnemonics (short names such as LDD, ADD) and labels instead of binary, so it is easier for people to read and write. There is a one-to-one relationship between assembly instructions and machine code instructions, and an assembler translates it to machine code. Both are machine dependent: they are specific to a particular processor.

The two-pass assembler

An assembler usually works in two passes over the source code:

• First pass: read the program line by line; build a symbol table that lists every label and variable name with its memory address; remove comments and blank lines. Instructions are not yet translated, because a jump may refer to a label further down that has not been seen yet (a forward reference).
• Second pass: translate each mnemonic to its opcode, replace each label or symbol with its address (using the symbol table), and produce the object code (machine code).

Instruction groups and the instruction set

Instructions are grouped by what they do: data movement (load, store, move), input and output, arithmetic (add, subtract, increment, decrement), comparison, conditional and unconditional jumps, and logical/bitwise operations and shifts. The exam provides an instruction set like the one below in each question that needs it, using one accumulator (ACC) and an index register (IX):

In the exam's number notation: #123 is denary, B01001010 is binary and &4A is hexadecimal.

Modes of addressing

• Immediate: the operand is the value to use. LDM #5 puts 5 in ACC.
• Direct: the operand is the address of the value. LDD 200 loads the value stored at address 200.
• Indirect: the operand is the address of a location that holds the address of the value. LDI 200 goes to address 200, finds an address there (say 350), and loads the value stored at 350. Used for pointers and tables.
• Indexed: the address used is the operand plus the value in IX. If IX holds 3, LDX 100 loads from address 103. Used for arrays: change IX to move through the elements.
• Relative: the address is found by adding an offset to the current address (the PC), used for short jumps. It makes code position independent.

Tracing an assembly program

Use a trace table with a column for each register and each memory location that changes. Execute one instruction at a time, and write the new value of anything it changes.

Example: memory 100 holds 5, 101 holds 8.

LDD 100     // ACC <- 5
ADD 101     // ACC <- 5 + 8 = 13
STO 102     // memory 102 <- 13
END

A loop example: counting down using a compare and a conditional jump.

      LDM #3
loop: SUB #1
      CMP #0
      JPN loop       // jump back while ACC is not 0
      END

ACC takes the values 3, 2, 1, 0 as the loop runs and the program ends when ACC is 0. In the trace table, write the result of every CMP too, because JPE/JPN use it.

4.3 Bit manipulation

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Bitwise operations on the byte 10110110: AND with 00001111 keeps the low four bits, OR with 00001000 sets bit 3, XOR with 00001111 flips the low four bits; and logical shifts, where a left shift of 2 turns 12 into 48 and a right shift of 3 turns 48 into 6

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Binary shifts

A shift moves every bit a number of places left or right. Empty places are filled with 0 in a logical shift. In the exam's assembly language, LSL #n shifts the bits in ACC n places to the left and LSR #n n places to the right.

• A left shift of one place multiplies an unsigned binary number by 2: 00000110 (6) becomes 00001100 (12).
• A right shift of one place divides by 2 (the bit shifted off the right-hand end is lost): 00001100 (12) becomes 00000110 (6).
• Shifting by n places multiplies or divides by $2^n$.
• Bits shifted off the end are lost, so a left shift can cause overflow and a right shift of an odd number loses the remainder.

An arithmetic shift keeps the sign bit in a two's complement number so that negative numbers stay negative when halved (the sign bit is copied into the vacated place). A cyclic (rotate) shift moves the bit that falls off one end into the other end, so no bits are lost.

Bitwise operations: masking

Bitwise instructions apply a logic operation to each pair of bits (one from ACC and one from the operand). In the exam notation: AND #n/AND <address>, OR #n/OR <address> and XOR #n/XOR <address> (the operand can also be given as Bn binary or &n hex).

Use a mask, a binary pattern chosen to change only the bits you want:

To test whether a particular bit (say bit 3, counting from 0 on the right) is on, use AND B00001000: the result is non-zero if the bit is 1. Combine with CMP #0 and a jump.

Monitoring and controlling a device

Many devices use the individual bits of a byte to represent separate on/off switches or sensor states: for example, bit 0 = pump, bit 1 = heater, bit 2 = alarm. A program can then:

• read a sensor bit with AND and a mask, and
• turn on an output with OR and a mask, turn off an output with AND and the inverted mask, or toggle it with XOR,

without changing the other bits in the same byte.