Computer Science (AS & A Level) · Oct / Nov 2022 · Paper 13 · Question 6

The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX). Instruction Explanation Opcode Operand LDM #n Immediate addressing. Load the number n to ACC LDD <address> Direct addressing. Load the contents of the location at the given address to ACC LDX <address> Indexed addressing. Form the address from <address> + the contents of the index register. Copy the contents of this calculated address to ACC LDR #n Immediate addressing. Load the number n to IX MOV <register> Moves the contents of the accumulator to the given register (IX) STO <address> Store contents of ACC at the given address ADD <address> Add the contents of the given address to the ACC ADD #n Add the denary number n to the ACC SUB #n Subtract the denary number n from the ACC INC <register> Add 1 to the contents of the register (ACC or IX) JMP <address> Jump to the given address CMP #n Compare the contents of ACC with number n CMI <address> Indirect addressing. The address to be used is at the given address. Compare the contents of ACC with the contents of this second address JPE <address> Following a compare instruction, jump to <address> if the compare was True JPN <address> Following a compare instruction, jump to <address> if the compare was False OUT Output to the screen the character whose ASCII value is stored in ACC END Return control to the operating system <address> can be an absolute or a symbolic address # denotes a denary number, e.g. #123 B denotes a binary number, e.g. B01001101

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