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Computer Science · May / June 2026 · Paper 11 · Question 2

0478

As printed in the paper

The question as text

A smartphone has a quad-core 2.4 GHz processor.

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  • 2(a)(i)[1]

    One from:

    Program counter // PC
    Memory Address register // MAR

  • 2(a)(ii)[3]

    Three from:

    The instruction is sent/copied to the current instruction

    register/CIR/control unit/CU // The CIR/CU receives the instruction // The CIR stores/holds the instruction …

    … from the memory data register/MDR
    The control unit/CU decodes the instruction
    An instruction set is used (to decode the instruction)
    The instruction is decoded/converted into the Opcode and Operand

  • 2(a)(iii)[1]

    One from:

    Arithmetic logic unit // ALU
    Accumulator // ACC
    Control unit // CU
    (Data/address/control) bus
    Memory data register // MDR
    Memory address register // MAR
    Program counter // PC
    Random access memory // RAM

  • 2(b)[2]

    Two from:

    It can execute more instructions/FDE/FE/clock cycles simultaneously // four instructions/FDE/FE/clock cycles can be executed

    simultaneously rather than two

    It can execute more instructions/FDE/FE/clock cycles per second
    … as it has double the number of cores // It has twice as many cores // It has more cores // It has 4 cores instead of 2 cores

  • 2(c)(i)[2]

    Two from:

    For example:

    Touchscreen
    Microphone
    Keyboard/keypad
    Button
    Sensor
    (Digital) camera

  • 2(c)(ii)[2]

    Two from:

    For example:

    Screen // touchscreen
    Speaker
    LED // light
    Actuator
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