Computer Science · Oct / Nov 2025 · Paper 12 · Question 4

0478

As printed in the paper

The question as text

A computer with a Von Neumann architecture has a central processing unit (CPU) that performs the fetch–decode–execute (FDE) cycle.

Read automatically from the paper; the printed page above is exact.

Show the answer and mark scheme

4(a)[5]
One mark for each correct part of the diagram.
The diagram shows:
CIR is built into CU
CIR stores instruction
CU decodes the instruction
Instruction is decoded using an instruction set // Instruction is separated into opcode and operand
Signal is sent from CIR to ALU (to execute)
CU sends signal to RAM to fetch any data needed for instruction
ACC is built into ALU
ACC stores any data needed for instruction
ALU executes the instruction // ALU performs the mathematic/logical operation (needed by the instruction) Example:
CU uses an instruction set
control unit (CU)
to decode instruction and
arithmetic logic
sends a signal to ALU to
unit (ALU)
execute the instruction
CIR
ACC
ACC stores data needed
Instruction is
to execute instruction
stored in CIR
4(b)[2]
Any two from:
Independent/self-contained processing unit
It executes/processes instructions // It performs the FDE cycle
It contains registers/units (to process data)
4(c)[4]
Four from (MAX 2 if no expansion given):
The number of cores could be increased // by example …
… this means that more instructions can be processed simultaneously
The clock speed could be increased // by example …
… this means that more instructions can be processed (by a core) per second
The cache could be increased // by example …
… this means that more frequently used data/instructions can be stored (to be accessed faster than RAM)

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