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Computer Science · Oct / Nov 2024 · Paper 11 · Question 5

0478

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The question as text

A central processing unit (CPU) performs the fetch–decode–execute (FDE) cycle.

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  • 5(a)[2]

    Any two from:

    Program counter // PC
    Memory address register // MAR
    Memory data register // MDR
    Current instruction register // CIR

  • 5(b)[3]

    Any three from:

    CIR/CU receives the instruction from the MDR // Instruction sent from MDR to CIR/CU
    … using the data bus
    Instruction is separated into opcode and operand
    Control unit decodes the instruction
    … using an instruction set

  • 5(c)[1]

    Any one from:

    Accumulator
    Memory address register // MAR
    Memory data register // MDR

  • 5(d)[3]

    data
    address
    control

  • 5(e)[2]

    It can now execute more instructions/FDE per second
    … this will increase the performance of the CPU
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